7.13. Overview: High Voltage Interlock Driver - HvilDrvr
Id |
HvilDrvr |
Title |
High Voltage Interlock Driver |
System |
High Voltage Power |
Document Type |
Application Software Component Specification Preview |
7.13.1. Overview
The High Voltage Interlock Driver (HvilDrvr) is a software component that monitors the status of the high voltage interlock (HVIL) circuit and provides the status to other components in the high voltage power system. The HVIL is a safety critical circuit that ensures the high voltage system is properly isolated when not in use.
7.13.2. Functions
Title |
Description |
|
|---|---|---|
1 |
Monitor HVIL Resistance |
Reads the HVIL resistance signal from the HVIL driver hardware. Validates the signal is in expected range and checks for oscillations or invalid values. |
2 |
Determine HVIL Status |
Determines the overall status of the HVIL circuit based on the validated resistance value and the current vehicle state. Possible states are: Initializing, Normal, Open Circuit, Short Circuit, Fault. |
3 |
Provide Component Status |
Maps the overall HVIL status to individual status values for each high voltage component in the system. Provides these as an output message to the HVPS. |
4 |
Trigger Diagnostics |
Monitors for HVIL resistance faults, vehicle state faults, and communication faults. Triggers the appropriate diagnostic trouble codes if any faults are detected. |
7.13.3. Ports
Id |
Direction |
Data Type |
Dimensions |
Unit |
|
|---|---|---|---|---|---|
1 |
VSM_State |
Incoming |
Enum: VtSig_VSM_State_t |
[-1] |
inherit |
2 |
VSM_State_valid |
Incoming |
boolean |
[-1] |
inherit |
3 |
VSM_Substate |
Incoming |
Enum: VtSig_VSM_Substate_t |
[-1] |
inherit |
4 |
HVIL_State |
Incoming |
Bus: CAN_HVIL_State_t |
[-1] |
inherit |
5 |
HVIL_State_valid |
Incoming |
boolean |
[-1] |
inherit |
6 |
HVPS_HVILStatus |
Outgoing |
Bus: CAN_HVPS_HVILStatus_t |
[-1] |
inherit |
7.13.4. Parameters
Id |
Data Type |
Dimensions |
Range |
Unit |
Description |
|
|---|---|---|---|---|---|---|
1 |
HvildrvHvilCanNoOfCycToChk |
uint16 |
[1,1] |
Min: 1, Max: 10 |
Number of CAN cycles to check to detct osciallation |
|
2 |
HvildrvHvilCanRxTiStep |
single |
[1,1] |
Min: 0.1, Max: 5 |
s |
CAN receive time step for HVIL signals |
3 |
HvildrvHvilOscnDetnThd |
single |
[1,1] |
Min: 0.5, Max: 1 |
Oscillation detection threshold |
|
4 |
HvildrvHvilRFltTiout |
single |
[1,1] |
Min: 0, Max: 30 |
sec |
HVIL resistance fault time threshold |
5 |
HvildrvHvilSigLowrLim |
single |
[1,1] |
Min: , Max: |
HVIL_Resistance Min out of range detection |
|
6 |
HvildrvHvilSigUpprLim |
single |
[1,1] |
Min: , Max: |
HVIL_Resistance Max out of range detection |
|
7 |
HvildrvVsmCanNoOfCycToChk |
uint16 |
[1,1] |
Min: 1, Max: 10 |
Number of CAN cycles to check to detct osciallation |
|
8 |
HvildrvVsmCanRxTiStep |
single |
[1,1] |
Min: 0.1, Max: 5 |
s |
CAN receive time step for VSM signals |
9 |
HvildrvVsmOscnDetnThd |
single |
[1,1] |
Min: 0.5, Max: 1 |
Oscillation detection threshold |
|
10 |
HvildrvHvilAbsvJmp |
single |
[1,1] |
Min: , Max: |
Ohm |
Abnormal jump Value |
11 |
HvildrvHvilIniTiout |
single |
[1,1] |
Min: 0, Max: 30 |
sec |
Maximum allowed time for HVIL line resistance signals be in SNA state |
12 |
HvildrvHvilFltLowrLim |
uint16 |
[1,1] |
Min: 0, Max: 10000 |
Ohm |
Resistance corresponding to an lower Error bound |
13 |
HvildrvHvilOkUpprLim |
uint16 |
[1,1] |
Min: 0, Max: 10000 |
Ohm |
Resistance corresponding to an higher Ok bound |
14 |
HvildrvVehDevCfg |
boolean |
[25,1] |
Min: 0, Max: 1 |
Turn on HV components that presents on vehicle |